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128Mb: x16 Mobile SDRAM
General Description
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time and the capability to randomly change column addresses on each clock cycle
during a burst access.
Figure 3:
8 Meg x 16 SDRAM Functional Block Diagram
BA1
0
0
1
BA0
0
1
0
Bank
0
1
2
CKE
1
1
3
CLK
CS#
WE#
CONTROL
LOGIC
CAS#
RAS#
BANK1
BANK2
BANK3
MODE REGISTER
REFRESH 12
COUNTER
ROW-
ADDRESS
12
BANK0
ROW-
BANK0
12
12
MUX
ADDRESS
LATCH
&
4096
MEMORY
ARRAY
(4,096 x 512 x 16)
2
2
LDQM,
UDQM
DECODER
SENSE AMPLIFIERS
4096
16
DATA
OUTPUT
REGISTER
2
I/O GATING
DQM MASK LOGIC
16
DQ0–
DQ15
A0–A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
READ DATA LATCH
WRITE DRIVERS
16
DATA
INPUT
COLUMN-
512
(x16)
COLUMN
DECODER
REGISTER
9
ADDRESS
COUNTER/
LATCH
9
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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